1. Field of the Invention
This invention relates to a random access memory (DRAM) device and, more particularly, To a structure and a method for fabricating an array of DRAM cells having pillar-shaped stacked capacitors with increased capacitance.
2. Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronic industry, and particularly in the computer industry for storing binary information. The DRAM circuit consists of an array of individual memory cells, each cell consisting of a single pass transistor, usually a field effect transistor (FET), and a storage capacitor. Generally, peripheral row decoder circuits are used to select and access the memory cells via the word lines and pass transistors, and column decoder and read/write circuits are used to store and retrieve binary information in the form of charge on the storage capacitor.
In recent years there has been a dramatic increase in the number of memory cells on a DRAM chip. For example, the cell count on a chip is currently about 64 million, and is expected to reach about 256 million cells (bits) by the year 1998. This increase in the number of cells on a DRAM chip is also expected to increase by a factor of 4 about every 3 years for the foreseeable future. This increase in cell density is a result of down sizing of the individual devices with resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching and other semiconductor technology innovations, such as forming self-aligning structures, shallow implantations, and similar techniques. However, this device down sizing is putting additional demands on the electrical requirements of the semiconductor devices. For example, the rapid increase in the number of cells on the DRAM chip and the corresponding decrease in physical size of the capacitor has made it increasingly difficult to store sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. Also, if the value of the capacitance is not maintained, then these volatile storage cells also require more frequent refresh cycles to maintain the charge on the capacitor.
Because the storage capacitor must occupy an area limited by the cell size, so as to accommodate the array of capacitors on the chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface.
One proposed method is to form a trench capacitor by etching trenches in the semiconductor substrate, but unfortunately, as the cell area decreases area it becomes increasing difficult to built the FET and the capacitor in the same substrate cell area. An alternative approach is to use stacked capacitors that are formed on the surface over the FET and within the cell area. These stacked capacitors have received considerable interest in recent years because of the variety of ways that its shape can be controlled in the third dimension to increase the capacitance surface area without increasing the area it occupies on the substrate. Many three-dimensional stacked capacitors having various shapes have been reported in the recent literature, such as fin-shaped, conical shaped, fork-shaped, and the likes have been reported in which the bottom electrode is patterned over the cell area. For example, one method for forming a DRAM device having fork-shaped is described by Y. Park, et al, U.S. Pat. No. 5,332,685, in which contact plugs are formed concurrent for the bottom electrodes of the stacked capacitors and the bit line interconnects, and then both the capacitors and bit lines are formed adjacent to each other. This, however, restricts the capacitor area and necessitates the need for design ground rules that limit the cell area.
On future DRAM devices with very high cell density, it becomes increasingly difficult to align and pattern the capacitor electrode over the cell area that provide sufficient increase in capacitance. Therefore, there is still a very strong need in the semiconductor industry to provide alternative methods for making stacked capacitors that occupy even smaller lateral area on the substrate while providing sufficient capacitance to satisfy the above sign-to-noise ratio requirements.